Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.


software_version_and_target_device
betaFALSE build_version2258646
date_generatedSat Oct 27 09:09:37 2018 os_platformLIN64
product_versionVivado v2018.2 (64-bit) project_id225a1dafe7da4b1290d62d328b9c4dde
project_iteration20 random_id5e2e585c-b098-473a-8dac-3c952e63f48f
registration_id207600273_1777503595_210590801_420 route_designTRUE
target_devicexc7a50t target_familyartix7
target_packageftg256 target_speed-1
tool_flowVivado

user_environment
cpu_nameAMD FX(tm)-8120 Eight-Core Processor cpu_speed1510.944 MHz
os_nameUbuntu os_releaseUbuntu 16.04.5 LTS
system_ram8.000 GB total_processors1

vivado_usage
gui_handlers
abstractsearchablepanel_show_search=1 addsrcwizard_specify_hdl_netlist_block_design=1 basedialog_cancel=8 basedialog_no=1
basedialog_ok=30 basedialog_yes=1 constraintschooserpanel_create_file=1 copyrundialog_run_name=1
coretreetablepanel_core_tree_table=7 createconstraintsfilepanel_file_name=1 createsrcfiledialog_file_name=5 createsrcfiledialog_file_type=4
definemodulesdialog_define_modules_and_specify_io_ports=19 filesetpanel_file_set_panel_tree=201 flownavigatortreepanel_flow_navigator_tree=24 fpgachooser_category=3
fpgachooser_family=3 fpgachooser_fpga_table=6 fpgachooser_package=5 fpgachooser_speed=3
fpgachooser_temperature=1 hcodeeditor_search_text_combo_box=1 languagetemplatesdialog_templates_tree=7 mainmenumgr_checkpoint=1
mainmenumgr_edit=2 mainmenumgr_file=12 mainmenumgr_flow=6 mainmenumgr_ip=2
mainmenumgr_open_recent_project=2 mainmenumgr_project=6 mainmenumgr_reports=12 mainmenumgr_settings=2
mainmenumgr_tools=12 mainmenumgr_view=2 mainmenumgr_window=8 mainwinmenumgr_layout=4
msgtreepanel_message_view_tree=24 msgview_critical_warnings=3 msgview_error_messages=3 msgview_information_messages=2
msgview_warning_messages=4 pacommandnames_add_sources=8 pacommandnames_auto_connect_target=16 pacommandnames_auto_update_hier=19
pacommandnames_close_project=1 pacommandnames_language_templates=1 pacommandnames_new_project=2 pacommandnames_open_hardware_manager=6
pacommandnames_open_ip_location=1 pacommandnames_read_sio_scan=1 pacommandnames_run_bitgen=11 pacommandnames_set_as_top=1
pacommandnames_simulation_live_restart=1 pacommandnames_simulation_live_run=12 pacommandnames_simulation_relaunch=2 pacommandnames_simulation_reset=3
pacommandnames_simulation_run=8 pacommandnames_simulation_run_behavioral=3 pacommandnames_src_replace_file=3 pacommandnames_toggle_view_nav=5
paviews_code=31 paviews_ip_catalog=1 paviews_project_summary=7 planaheadtab_show_flow_navigator=2
programdebugtab_open_target=15 programdebugtab_program_device=20 programfpgadialog_program=19 progressdialog_background=1
projectnamechooser_choose_project_location=1 projectnamechooser_project_name=1 rdicommands_delete=1 rdicommands_line_comment=2
rdicommands_save_file=3 rdicommands_waveform_save_configuration=4 rdiviews_waveform_viewer=10 removesourcesdialog_also_delete=1
settingsprojectgeneralpage_choose_device_for_your_project=1 simulationliverunforcomp_specify_time_and_units=3 simulationscopespanel_simulate_scope_table=7 srcchooserpanel_add_files_below_to_this_simulation_set=1
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1 srcchooserpanel_create_file=6 srcfileproppanels_type=1 srcmenu_ip_hierarchy=18
stalemoreaction_out_of_date_details=1 stalerundialog_no=1 statemonitor_reset_run=2 syntheticagettingstartedview_recent_projects=8
syntheticastatemonitor_cancel=6 taskbanner_close=17 touchpointsurveydialog_yes=1 waveformnametree_waveform_name_tree=25
java_command_handlers
addsources=8 autoconnecttarget=16 closeproject=1 coreview=1
customizecore=2 editdelete=1 editpaste=2 editundo=1
launchprogramfpga=19 newproject=2 openhardwaremanager=16 openiplocationhandler=1
openrecenttarget=1 runbitgen=27 savefileproxyhandler=9 settopnode=1
showview=1 simulationrelaunch=2 simulationrestart=1 simulationrun=3
simulationrunfortime=12 toggleviewnavigator=5 toolssettings=1 toolstemplates=1
updatesourcefiles=3 waveformsaveconfiguration=4 writesioscan=1
other_data
guimode=8
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=7 simulator_language=Verilog srcsetcount=7 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 carry4=6 fdre=66 gnd=3
ibuf=3 lut2=12 lut3=9 lut4=6
lut5=17 lut6=47 obuf=1 obuft=8
vcc=6
pre_unisim_transformation
bufg=1 carry4=6 fdre=66 gnd=3
ibuf=3 lut2=12 lut3=9 lut4=6
lut5=17 lut6=47 obuf=1 obuft=8
vcc=6

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
timing-17=66

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") confidence_level_clock_activity=Low confidence_level_design_state=High
confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low confidence_level_overall=Low
customer=TBD customer_class=TBD devstatic=0.081181 die=xc7a50tftg256-1
dsp_output_toggle=12.500000 dynamic=3.279189 effective_thetaja=4.9 enable_probability=0.990000
family=artix7 ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile)
i/o=2.586357 input_toggle=12.500000 junction_temp=41.3 (C) logic=0.355006
mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000
netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=3.360371 output_enable=1.000000
output_load=5.000000 output_toggle=12.500000 package=ftg256 pct_clock_constrained=1.460000
pct_inputs_defined=0 platform=lin64 process=typical ram_enable=50.000000
ram_write=50.000000 read_saif=False set/reset_probability=0.000000 signal_rate=False
signals=0.337827 simulation_file=None speedgrade=-1 static_prob=False
temp_grade=commercial thetajb=8.2 (C/W) thetasa=4.6 (C/W) toggle_rate=False
user_board_temp=25.0 (C) user_effective_thetaja=4.9 user_junc_temp=41.3 (C) user_thetajb=8.2 (C/W)
user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000
vccadc_voltage=1.800000 vccaux_dynamic_current=0.094482 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.013332 vccaux_total_current=0.107814
vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000294 vccbram_total_current=0.000294
vccbram_voltage=1.000000 vccint_dynamic_current=0.700832 vccint_static_current=0.017590 vccint_total_current=0.718422
vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000
vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000
vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000
vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000
vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000
vcco25_voltage=2.500000 vcco33_dynamic_current=0.729785 vcco33_static_current=0.001000 vcco33_total_current=0.730785
vcco33_voltage=3.300000 version=2018.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=120 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=75 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=150 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=75 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=6
fdre_functional_category=Flop & Latch fdre_used=66 ibuf_functional_category=IO ibuf_used=3
lut2_functional_category=LUT lut2_used=13 lut3_functional_category=LUT lut3_used=9
lut4_functional_category=LUT lut4_used=7 lut5_functional_category=LUT lut5_used=17
lut6_functional_category=LUT lut6_used=45 obuf_functional_category=IO obuf_used=1
obuft_functional_category=IO obuft_used=8
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=32600 lut_as_logic_fixed=0 lut_as_logic_used=81 lut_as_logic_util_percentage=0.25
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=65200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=66 register_as_flip_flop_util_percentage=0.10
register_as_latch_available=65200 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=32600 slice_luts_fixed=0 slice_luts_used=81 slice_luts_util_percentage=0.25
slice_registers_available=65200 slice_registers_fixed=0 slice_registers_used=66 slice_registers_util_percentage=0.10
fully_used_lut_ff_pairs_fixed=0.10 fully_used_lut_ff_pairs_used=0 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=32600 lut_as_logic_fixed=0 lut_as_logic_used=81 lut_as_logic_util_percentage=0.25
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=50
lut_ff_pairs_with_one_unused_lut_output_fixed=50 lut_ff_pairs_with_one_unused_lut_output_used=52 lut_flip_flop_pairs_available=32600 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=52 lut_flip_flop_pairs_util_percentage=0.16 slice_available=8150 slice_fixed=0
slice_used=31 slice_util_percentage=0.38 slicel_fixed=0 slicel_used=22
slicem_fixed=0 slicem_used=9 unique_control_sets_used=8 using_o5_and_o6_fixed=8
using_o5_and_o6_used=10 using_o5_output_only_fixed=10 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=71
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=139821 bogomips=7247 bram18=0 bram36=0
bufg=0 bufr=0 ctrls=8 dsp=0
effort=2 estimated_expansions=77316 ff=66 global_clocks=1
high_fanout_nets=0 iob=12 lut=81 movable_instances=185
nets=208 pins=1008 pll=0 router_runtime=0.000000
router_timing_driven=1 threads=8 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a50tftg256-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=main -verilog_define=default::[not_specified]
usage
elapsed=00:00:36s hls_ip=0 memory_gain=480.984MB memory_peak=1662.887MB

xsim
command_line_options
-sim_mode=behavioral -sim_type=default::